Side-channel attacks are critical as they, despite the mathematical security of the algorithm, break the security assumption that private data stays hidden from the adversary. Developing secure hardware can be expensive, as multiple iterations of prototyping may be required to achieve a satisfactory level of security against side-channel attacks. Currently, the fairly new and open-source CPU-platform RISC-V is gaining traction by entering the IoT- and consumer market and also gains interest in security oriented projects such as OpenTitan. In case of security-critical applications, especially when the hardware is exposed to third party, the implementations of cryptographic algorithms must be secure against side-channel attacks. For the RISC-V platform currently only a small number of tools exist to assess the probing security. Further, we could identify a lack of simulation-based tooling to do so, with the ability to analyze larger implementations as e.g., full ciphers. To address this demand, we use PROLEAD_SW as a starting point and extend it to support the RISC-V platform. By analyzing micro-architectural leakage effects on the RISC-V platform we show that the CPU-independent leakage model used by PROLEAD_SW for the ARM architecture is suitable for the RISC-V platform. To verify the correctness of the new tooling, test-vectors are executed with the new tooling. In a final step, the performance of the new tooling is compared to the performance of the original version of PROLEAD_SW by analyzing two masked AES C implementations with both tools.